Qualcomm Design Verification Engineer in Shanghai, China
Job Id E1962623
Job Title Design Verification Engineer
Post Date 02/08/2018
Company-Division Qualcomm Atheros Inc
Qualcomm Atheros at http://www.qualcomm.com/about/businesses/qca
Job Area Engineering - Verification
Location China - Shanghai
Job Overview Define testbench infrastructure using System Verilog, UVM and maybe Formal. Assist in complete verification of high performance, high speed, low power ASIC. Work closely with system architect and design managers to architect a new design verification environment and produce high quality verification closure. Guide the development of comprehensive, flexible, and portable block to chip level testbench, detailed test plans and coverage closure. Experienced in Touch Screen, DSP, SOC or mix signal simulation is a big plus. Infrastructure work including developing scripts, methodologies and tools for efficiency and quality improvements.
Minimum Qualifications UVM based verification flow.
Familiar with Perl/Python, Makefile, C.
Assertion and formal verification.
Low power verification.
Test bench bug tracking and regression mechanism.
Be able to setup verification strategies based on directed and random testing.
Code and functional coverage-driven verification.
Past experience of successfully technically guiding complex, high speed design verification.
Preferred Qualifications NA
Education Requirements MS/EE or CS with 3+ years of relevant experience
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.