Qualcomm Sr. Digital Design Engineer--SDC Digital in Shanghai, China

Job Description:

Job Id E1956381

Job Title Sr. Digital Design Engineer--SDC Digital

Post Date 08/18/2017

Company-Division Qualcomm Atheros Inc


Qualcomm Atheros at http://www.qualcomm.com/about/businesses/qca

Job Area Engineering - Hardware

Location China - Shanghai

Job Overview The Digital Design Engineer will be responsible for designing our wireless and SOC ASIC's. You will work closely with our architecture/algorithm engineers to explore ideas for next generation products and then develop RTL to turn these ideas into customer solutions.

Duties/Responsibilities:

Chip features specification and RTL design

Lint, CDC, Synthesis, verification, timing sign-off.

FPGA emulation, lab validation and debugging.

Minimum Qualifications MS in Electrical/Electronics Engineering

At least 3 years hands on experience with specification, micro-architecture, design, Verilog RTL coding, verification

Proficient in the use of industry standard languages and flows for RTL coding, synthesis, functional verification, timing analysis, and scripting.

Nice to have a proven record of delivering successful ASICs from functional specification to the final product.

One or more advantages as following are highly desirable: Hands on experience in WLAN MAC design and familiar with IEEE802.11 standard; A strong background in digital communication, signal processing and networking protocols; IC Design experiences in wireless communications; Experiences with ARM/DSP, NoC/AXI/AHB bus and External memory controller development.

Excellent team and interpersonal skills

Clear written and verbal communication.

Good communication skills in English.

Desired to have cross-functional experience interacting with software, verification, and physical design teams.

Preferred Qualifications Must be proficient in RTL coding, Lint/CDC checking, logic synthesis, block/chip level timing analysis.

Good knowledge of IC design backend flows.

Experiences in IC life-cycle from conception, design, verification, top-level netlist with pads to tape-out, chip-testing and mass-production is a plus.

Familiar with pre-silicon and post-silicon validation of ASIC designs is a plus

FPGA or embedded SW skill is a plus.

Education Requirements NA.

EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.