Mentor, A Siemens Business Associate Application Engineer - MED - 6395 in Shanghai, China

Associate Application Engineer - MED - 6395


Description

Company: Mentor Graphics

Job Title: Associate Application Engineer – MED - 6395

Job Location: China – Shanghai

Job Category: College

Job Duties:

Mentor, a Siemens Business is now inviting applications for our Associate / Graduate Program for the position of Associate

Applications Engineer – MED.

In this position, you will be involved in a structured Associate Engineer Training Program. This is a fast-track training program that challenges you to develop the expertise needed to solve difficult technical problems and the commercial skills needed to work with customers within the region.

Associate Applications Engineers join us as members of a team of highly motivated individuals working with customers designing the most complex hardware and software systems in the world and whose applications span the electronics industry. This training program will give you unique insight into our product marketing divisions and sales organization and the opportunity to work with and learn from industry experts.

Upon successful completion of the program, you will be eligible to progress into an Application Engineer role, focusing on developing technical relationships at the engineering level with customers including customer presentations, needs analysis, product demonstrations, and coordination of benchmarking and evaluation activities.

Job Qualifications:

New Graduate (2018) BS/MS (Masters degree is preferred) in Electrical or Computer Engineering. Programming skills in C/C++, Tcl/TK, PERL as well as an understanding of object oriented concepts as applied to a Verification Environment. Coursework/Experience with HDL-based, register-transfer-level (RTL), digital logic design, verification languages, and functional verification methodology, for ASICs and/or FPGAs. This experience/coursework should include some or all of the following: testbench architecture, design and implementation using UVM/OVM/AVM verification methodology, VHDL and/or Verilog HDL simulation, SystemVerilog, Specman/e, Vera and/or PSL and Assertion-Based Verification techniques. Experience in constrained random directed testing, is also desirable.